1. Field of the Invention
This invention relates generally to methods of testing semiconductor memory devices. More specifically, this invention relates to a method of testing semiconductor memory devices that utilizes parallel march patterns that substantially increase testing speed.
2. Discussion of the Related Art
The rapid growth of technological requirements and the worldwide acceptance of sophisticated electronic device have created an unprecedented demand for large-scale, complex, integrated circuits. Meeting these demands has required technological advances in materials and processing equipment and a significant increase in the number of individuals involved in integrated circuit design and testing. In addition, there has been an increased emphasis on effectively utilizing sophisticated test instruments and procedures to aid in the analysis of the manufacturing parameters so that the design and manufacturing process can be improve and in the testing of semiconductor devices before the devices are shipped to customers.
In order to meet the increasing demand, there has been an ever-increasing requirement to increase the density of devices manufactured in a semiconductor device. The number of devices manufactured on a chip exceeded the generally accepted definition of VLSI (very large scale integration) of more than 100,000 devices per chip in the mid-1970s. By 1986, this number of devices manufactured on a chip had grown to over 1 million devices per chip. As is well known, today the number of devices per chip is well over 1 million devices per chip and is still growing at an exponential rate.
To keep up with the growing demand for technological growth, there has been a concomitant demand for a growth in the size of memory devices. Large memory devices are one of the keys to the continued growth of technology. Memory devices have grown dramatically with some memory devices being manufactured with multiple millions of memory bits. It is the practice and a requirement of the semiconductor industry to test each memory bit in the memory device before it is sent to a customer. One current method of testing memory is known as the serial march method of testing. In this method, a selected number of consecutive memory bits are programmed logic high and adjacent logic low memory bits are read to determine if they have changed state due to leakage or a short from the programmed logic high memory bits. The selected number of memory bits is moved one bit and the reading of the adjacent logic low memory bits is repeated. This process continues until the entire memory device has been tested. As can be appreciated, the number of clock cycles needed to test the memory device is approximately equal to the number of memory bits in the memory device. For example, a memory device having 1 million memory bits would require approximately 1 million clock cycles to completely test the memory device. As the memory devices have grown, the number of required clock cycles to test has grown at the same pace.
While the time to test a memory device completely has increased, at the same time the price of the memory devices has decreased. The decease in the selling price of the memory devices has caused increased pressure upon the testing facility to decrease the cost of testing.
Therefore, what is needed is a method to test memory devices that is rapid, cost effective, and thorough.